Arduino et plus

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity diviseur is
	Generic(N : positive := 50000000);
	port (
		clk: in STD_LOGIC;
		reset: in STD_LOGIC;
		tc_out: out STD_LOGIC
	);
end diviseur;

architecture arch_diviseur of diviseur is

signal cpt : std_logic_vector(31 downto 0) := x"00000000";
signal tc : std_logic;

constant max : positive := N-1;

begin
	tc_out <= tc;
	comptage: process(clk,reset)
	begin
		if reset = '0' then
			cpt <= (others => '0');
		else
			if rising_edge(clk) then 
				if cpt < max then
					cpt <= cpt + 1;
				else	
					cpt <= (others => '0');
				end if;
			end if;	
		end if;
	end process comptage;
	retenue: process(cpt)
	begin
		if cpt= max then
			tc <= '1';
		else 
			tc <='0';
		end if;
	end process retenue; 

end arch_diviseur;
					

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity chenillard is
	port (
		iCLK: in STD_LOGIC;
		iRESETn: in STD_LOGIC;
		bMKR_Q: out STD_LOGIC_VECTOR(0 to 7));
end chenillard;

architecture arch_chenillard of chenillard is

component diviseur is
    Generic(N : positive := 50000000);
    Port ( 	clk : in  STD_LOGIC;
				reset: in STD_LOGIC;
				tc_out : out STD_LOGIC);
end component;

signal tc : STD_LOGIC ;
signal qreg : STD_LOGIC_VECTOR(0 to 7);
constant division : positive := 10000000 ;

begin

	div1s: diviseur generic map (N => division)
			port map(clk => iCLK, reset => iRESETn , tc_out => tc);

	bMKR_Q <= qreg;
	
	registres: process(iCLK,tc,iRESETn)
	begin
		if iRESETn = '0' then
			qreg <= ( 0 => '1', others => '0');
		elsif tc = '1' then
			if rising_edge(iCLK) then
				qreg <= qreg(7) & qreg(0 to 6);
			end if;
		end if;
	end process registres;
   							
end arch_chenillard;
					

Pour comprendre le code VHDL, il faut se reporter au chapitre qui décrit ce langage.

#include <wiring_private.h>
#include "jtag.h"

#define TDI                               12
#define TDO                               15
#define TCK                               13
#define TMS                               14
#define MB_INT                            28
#define MB_INT_PIN                        31
#define SIGNAL_OUT                        41 //B5 L16
#define SIGNAL_IN                         33 //B2 N2

#define no_data    0xFF, 0xFF, 0xFF, 0xFF, \
          0xFF, 0xFF, 0xFF, 0xFF, \
          0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
          0xFF, 0xFF, 0xFF, 0xFF, \
          0x00, 0x00, 0x00, 0x00  \

#define NO_BOOTLOADER   no_data
#define NO_APP        no_data
#define NO_USER_DATA    no_data

__attribute__ ((used, section(".fpga_bitstream_signature")))
const unsigned char signatures[4096] = {
  //#include "signature.ttf"
  NO_BOOTLOADER,

  0x00, 0x00, 0x08, 0x00,
  0xA9, 0x6F, 0x1F, 0x00,   // Don't care.
  0x20, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x65, 0x73, 0x2d, 0x65, 0x6d, 0x62, 0x61, 0x72, 0x71, 0x75, 0x65, 0x73, 0x2e, 0x66, 0x72, 0x20, 0x00, 0x00, 0xff, 0xf0, 0x0f,
  0x01, 0x00, 0x00, 0x00,   
  0x01, 0x00, 0x00, 0x00,   // Force

  NO_USER_DATA,
};
__attribute__ ((used, section(".fpga_bitstream")))
const unsigned char bitstream[] = {
  #include "app.h"
};

//========== declarations application ==========================
#define DEMI_PERIODE 500
#define CLIGNOTANT 8  
//==============================================================

void setup() {

  int ret;
  uint32_t ptr[1];

  //enableFpgaClock();
  pinPeripheral(30, PIO_AC_CLK);
  clockout(0, 1);
  delay(1000);
  
  //Init Jtag Port
  ret = jtagInit();
  mbPinSet();

  // Load FPGA user configuration
  ptr[0] = 0 | 3;
  mbEveSend(ptr, 1);

  // Give it delay
  delay(1000);

  // Configure onboard LED Pin as output
  pinMode(LED_BUILTIN, OUTPUT);

  // Disable all JTAG Pins (usefull for USB BLASTER connection)
  pinMode(TDO, INPUT);
  pinMode(TMS, INPUT);
  pinMode(TDI, INPUT);
  pinMode(TCK, INPUT);

  // Configure other share pins as input too
  pinMode(SIGNAL_IN, INPUT);  // oSAM_INT
  pinMode(MB_INT_PIN, INPUT);
  pinMode(MB_INT, INPUT);
  
  //========== setup application =================================
  pinMode(CLIGNOTANT,OUTPUT);
  //==============================================================

}

//========== loop application =================================
void loop() {
	digitalWrite(CLIGNOTANT,HIGH);
	delay(DEMI_PERIODE);
    digitalWrite(CLIGNOTANT,LOW);               
    delay(DEMI_PERIODE);
}
//==============================================================
			

Le code est copié à partir des exemples cités auparavant. Seul la gestion du clignotement d'une LED a été ajouté.

Code de l'encodage TMDS tmds.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity tmds is
	Port (  iclk 		: in STD_LOGIC;
		ictl 		: in STD_LOGIC_VECTOR(1 downto 0);
		iimagevisible 	: in STD_LOGIC ;
		idata 		: in STD_LOGIC_VECTOR(7 downto 0);
		otmds		: out STD_LOGIC_VECTOR(9 downto 0));
end tmds;

architecture architecture_tmds of tmds is

signal  ouex_data 	: std_logic_vector(7 downto 0);
signal  nouex_data 	: std_logic_vector(7 downto 0);
signal  xdata 		: std_logic_vector(7 downto 0);
signal  nbits_data 	: std_logic_vector(3 downto 0);
signal  nbits_xdata 	: std_logic_vector(3 downto 0);
signal  offset_datas 	: std_logic_vector(4 downto 0);
signal  ctl 		: std_logic_vector(1 downto 0);
signal  imagevisible 	: std_logic ;
signal  bit8 		: std_logic ;

begin
	nbits_data <= ( "000" & idata(0)) + ( "000" & idata(1)) + ( "000" & idata(2)) + ( "000" & idata(3)) + ( "000" & idata(4)) + ( "000" & idata(5)) + ( "000" & idata(6)) + ( "000" & idata(7));
	ouex_data(0) <= idata(0);
	xored: for i in 1 to 7 generate
		ouex_data(i) <= ouex_data(i-1) xor idata(i);
	end generate;
	nouex_data(0) <= not idata(0);
	xnored: for i in 1 to 7 generate
		nouex_data(i) <= nouex_data(i-1) xnor idata(i);
	end generate;
	
	calcul: process(iclk,iimagevisible) 
	begin
-- etape 1	
		if rising_edge(iclk) then
			imagevisible <= iimagevisible ;
			ctl <= ictl ;
			if ((nbits_data >  4) or ((nbits_data = 4) and (idata(0) = '0'))) then
				xdata <= nouex_data ;
				bit8 <= '0' ;
				nbits_xdata <= ( "000" & nouex_data(0)) + ( "000" & nouex_data(1)) + ( "000" & nouex_data(2)) + ( "000" & nouex_data(3)) + ( "000" & nouex_data(4)) + ( "000" & nouex_data(5)) + ( "000" & nouex_data(6)) + ( "000" & nouex_data(7));
			else
				xdata <= ouex_data ;
				bit8 <= '1' ;
				nbits_xdata <= ( "000" & ouex_data(0)) + ( "000" & ouex_data(1)) + ( "000" & ouex_data(2)) + ( "000" & ouex_data(3)) + ( "000" & ouex_data(4)) + ( "000" & ouex_data(5)) + ( "000" & ouex_data(6)) + ( "000" & ouex_data(7));
			end if;
-- etape 2
			if (imagevisible = '0') then -- controle hors partie visible
				offset_datas <= "00000" ;
				case ctl is
					when "00" =>  otmds <= "1101010100" ;
					when "01" =>  otmds <= "0010101011" ;
					when "10" =>  otmds <= "0101010100" ;
					when "11" =>  otmds <= "1010101011" ;
					when others => otmds <= "1101010100" ;
				end case;
			else -- data partie visible 
				if ((offset_datas = 0) or (nbits_xdata = 4)) then
					if (bit8 = '1') then
						otmds <= "01" & xdata ;
						offset_datas <= offset_datas + (nbits_xdata(3 downto 0) & "0") - 8;
					else
						otmds <= "10" & not xdata;
						offset_datas <= offset_datas - (nbits_xdata(3 downto 0) & "0") + 8;
					end if;
				else
					if (((signed(offset_datas) >= 0) and (nbits_xdata > 4)) or ((signed(offset_datas) < 0) and (nbits_xdata < 4))) then
						otmds <= '1' & bit8 & not xdata;
						offset_datas <= offset_datas + ( "000" & bit8 & '0' ) - (nbits_xdata(3 downto 0) & "0") + 8;
					else
						otmds<= '0' & bit8 & xdata;
						offset_datas <= offset_datas - ( "000" & (not bit8) & '0') + (nbits_xdata(3 downto 0) & "0") - 8;
					end if;
				end if;
			end if;
		end if;

	end process;

end architecture_tmds;
			

Code du module hdmi_interface.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hdmi_interface is
	port (
			clkpixel 	: in STD_LOGIC;
			clkdata 	: in STD_LOGIC;
			videoenable 	: in STD_LOGIC ;
			imagevisible 	: in STD_LOGIC;
			isynchroH 	: in STD_LOGIC;
			isynchroV 	: in STD_LOGIC;
			irouge 		: in STD_LOGIC_VECTOR(7 downto 0);
			ivert 		: in STD_LOGIC_VECTOR(7 downto 0);
			ibleu 		: in STD_LOGIC_VECTOR(7 downto 0);
			ohdmi_clk 	: out STD_LOGIC;
			ohdmi_datas 	: out STD_LOGIC_VECTOR(2 downto 0)
		);
end hdmi_interface;

architecture arch_hdmi_interface of hdmi_interface is

component tmds is
	Port (  iclk 			: in STD_LOGIC;
			ictl 		: in STD_LOGIC_VECTOR(1 downto 0);
			iimagevisible 	: in STD_LOGIC ;
			idata 		: in STD_LOGIC_VECTOR(7 downto 0);
			otmds		: out STD_LOGIC_VECTOR(9 downto 0)
			);
end component tmds;

component hdmi_sortie is
	Port
	(
		aclr		   	: in STD_LOGIC ;
		datain_h		: in STD_LOGIC_VECTOR (3 DOWNTO 0);
		datain_l		: in STD_LOGIC_VECTOR (3 DOWNTO 0);
		outclock		: in STD_LOGIC ;
		dataout			: out STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
end component hdmi_sortie;

signal tmds_rouge,tmds_vert,tmds_bleu, tmds_clk : std_logic_vector(9 downto 0);
signal hdmi_rouge, hdmi_vert, hdmi_bleu, hdmi_clk : std_logic_vector(9 downto 0);
signal data_rouge,data_vert,data_bleu : std_logic_vector(7 downto 0);
signal ctl_rouge, ctl_vert, ctl_bleu  : std_logic_vector(1 downto 0);
signal data_sortie_in_h , data_sortie_in_l : std_logic_vector(3 downto 0);
signal data_sortie_out : std_logic_vector(3 downto 0);

begin

	ctl_rouge <= "00" ;
	ctl_vert <= "00" ;
	ctl_bleu <= isynchroV & isynchroH ;
	data_rouge <= irouge ;
	data_vert <= ivert ;
	data_bleu <= ibleu ;
	
	chiptmdsrouge : tmds port map(iclk => clkpixel, ictl => ctl_rouge, iimagevisible => imagevisible, idata => data_rouge, otmds => tmds_rouge);
	chiptmdsvert : tmds port map(iclk => clkpixel, ictl => ctl_vert, iimagevisible => imagevisible, idata => data_vert, otmds => tmds_vert);
	chiptmdsbleu : tmds port map(iclk => clkpixel, ictl => ctl_bleu, iimagevisible => imagevisible, idata => data_bleu, otmds => tmds_bleu);
	
	serialisation : process(clkdata,videoenable)
	begin
		if videoenable = '0' then
			hdmi_clk <= "0000011111" ;
		else
			if rising_edge(clkdata) then
				if hdmi_clk = "0000011111" then
					hdmi_rouge <= tmds_rouge ;
					hdmi_vert <= tmds_vert ;
					hdmi_bleu <= tmds_bleu ;
				else
					hdmi_rouge <= "00" & hdmi_rouge(9 downto 2) ;
					hdmi_vert <= "00" & hdmi_vert(9 downto 2) ;
					hdmi_bleu <= "00" & hdmi_bleu(9 downto 2) ;
				end if;
				hdmi_clk <= hdmi_clk(1) & hdmi_clk(0)  & hdmi_clk(9 downto 2);
			end if ;
		end if ;
	end process serialisation;
	
-- sorties sur les fronts montants et descendants
	data_sortie_in_h  <= hdmi_clk(0) & hdmi_rouge(0) & hdmi_vert(0) & hdmi_bleu(0) ;
	data_sortie_in_l  <= hdmi_clk(1) & hdmi_rouge(1) & hdmi_vert(1) & hdmi_bleu(1) ;
	ohdmi_clk <= data_sortie_out(3) ;
	ohdmi_datas <= data_sortie_out(2 downto 0);
	chiphdmisortie : hdmi_sortie port map (aclr => '0' , datain_h => data_sortie_in_h , datain_l => data_sortie_in_l ,
											outclock => clkdata, dataout => data_sortie_out );

end arch_hdmi_interface;
			

Code du module hdmi_image.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity hdmi_image is
	port (
		clk 		: in STD_LOGIC;
		ienable		: in STD_LOGIC ;
		icptH 		: in STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		icptV 		: in STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		orouge 		: out STD_LOGIC_VECTOR(7 downto 0);
		overt 		: out STD_LOGIC_VECTOR(7 downto 0);
		obleu 		: out STD_LOGIC_VECTOR(7 downto 0)
		);
end hdmi_image;

architecture arch_hdmi_image of hdmi_image is

constant pasH : integer := 106 ;
constant valmax : integer := 211;

signal rouge, vert, bleu : std_logic_vector(7 downto 0);

begin

  orouge <= rouge ;
  overt <= vert ;
  obleu <= bleu ;
	
  picelsimage: process(clk,ienable)
  begin
   if falling_edge(clk) and ienable ='1' then
		if icptH < pasH then
			rouge <= std_logic_vector(to_unsigned(valmax,8)) ;
			vert  <= icptH(6 downto 0) & "0" ; -- kx
			bleu  <= x"00" ;
		elsif icptH < (2*pasH) then
			rouge <= valmax - (icptH(6 downto 0) & "0" - 2*pasH) ; -- valmx -k(x-pasH)
			vert  <= std_logic_vector(to_unsigned(valmax,8)) ;
			bleu  <= x"00" ;
		elsif icptH < (3*pasH) then
			rouge <= x"00" ;
			vert  <= std_logic_vector(to_unsigned(valmax,8)) ; 
			bleu  <= icptH(6 downto 0) & "0" -4*pasH ; -- k(x-2*pasH)
		elsif icptH < (4*pasH) then
			rouge <= x"00" ; 
			vert  <= valmax - (icptH(6 downto 0) & "0" -6*pasH) ; -- valmax - k(x-3*pasH)
			bleu  <= std_logic_vector(to_unsigned(valmax,8)) ;
		elsif icptH < (5*pasH) then
			rouge <= icptH(6 downto 0) & "0" -8*pasH ; -- k(x-4*pasH)
			vert  <= x"00" ;
			bleu  <= std_logic_vector(to_unsigned(valmax,8)) ;
		elsif icptH < (6*pasH) then
			rouge <= std_logic_vector(to_unsigned(valmax,8)) ; 
			vert  <= x"00" ;
			bleu  <= valmax - (icptH(6 downto 0) & "0" - 10*pasH)  ; -- valmax - k(x-5*pasH)
		else 
			rouge <= std_logic_vector(to_unsigned(valmax,8)) ; 
			vert  <= x"00" ;
			bleu  <= x"00" ;		
		end if ;
   end if;
  end process picelsimage;

end arch_hdmi_image;
			

Code du module hdmi_trame.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hdmi_trame is
	port (
		clk 		: in STD_LOGIC;
		ienable 	: in STD_LOGIC;
		ocptH 		: out STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		ocptV 		: out STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		ovisible 	: out STD_LOGIC;
		osynchroH 	: out STD_LOGIC;
		osynchroV 	: out STD_LOGIC
		);
end hdmi_trame;

architecture arch_hdmi_trame of hdmi_trame is

 constant HRES 		: integer := 640 ; -- 640
 constant HSS 		: integer := 656;  -- 656
 constant HSE 		: integer := 752;  --752
 constant Htotal 	: integer := 762 ; -- 800 ou 762 ??
 constant VRES 		: integer := 480 ; -- 480
 constant VSS 		: integer := 489; -- 489
 constant VSE 		: integer := 492; -- 492
 constant Vtotal 	: integer := 525 ; -- 525
 
 component compteur is
	Generic (N 	: integer := 10);
    Port ( clk 		: in  STD_LOGIC;
	   reset 	: in STD_LOGIC;
	   enable 	: in STD_LOGIC;
	   tc 		: out STD_LOGIC;
           Q 		: out  STD_LOGIC_VECTOR(11 downto 0));
end component compteur;
 
 
 signal cptH 		: std_logic_vector(11 downto 0);
 signal cptV 		: std_logic_vector(11 downto 0);
 signal cptHtc 		: std_logic;
 signal cptVenable 	: std_logic ;
 signal Hvisible	: std_logic ;
 signal Vvisible 	: std_logic ;

begin

	ocptH <= cptH ;
	ocptV <= cptV ;
	oVisible <= Hvisible and Vvisible ;
	
	chipcompteurH : compteur 	generic map (N => Htotal)
					port map (clk => clk , reset => ienable , enable => '1' , tc => cptVenable , Q => cptH );	
	
	chipcompteurV : compteur 	generic map (N => Vtotal)
					port map (clk => clk , reset => ienable , enable => cptVenable , tc => open ,  Q => cptV );	
	
  synchrosH: process(cptH) 
  begin
	if cptH >= HSS and cptH < HSE then
		osynchroH <= '1' ;
	else
		osynchroH <= '0' ;
	end if;
	if cptH < HRES  then
		Hvisible <= '1' ;
	else
		Hvisible <= '0' ;
	end if;
  end process synchrosH;
  
  synchrosV: process(cptV) 
  begin
	if cptV >= VSS and cptV < VSE then
		osynchroV <= '1' ;
	else
		osynchroV <= '0' ;
	end if;
	if cptV < VRES  then
		Vvisible <= '1' ;
	else
		Vvisible <= '0' ;
	end if;
  end process synchrosV;  

end arch_hdmi_trame;
			

Code du module hdmi_base.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hdmi_base is
	port (
		iCLK 		: in STD_LOGIC;
		iRESETn 	: in STD_LOGIC;
		iHDMI_HPD 	: in STD_LOGIC ;
		oHDMI_TX 	: out STD_LOGIC_VECTOR(0 to 2);
		oHDMI_CLK 	: out STD_LOGIC
	);
end hdmi_base;

architecture arch_hdmi_base of hdmi_base is

component hdmi_horloges is
	port
	(
		areset		: in STD_LOGIC  := '0';
		inclk0		: in STD_LOGIC  := '0';
		c0		: out STD_LOGIC ;
		c1		: out STD_LOGIC ;
		locked		: out STD_LOGIC 
	);
end component hdmi_horloges;

component hdmi_trame is
	port (
		clk 		: in STD_LOGIC;
		ienable 	: in STD_LOGIC;
		ocptH 		: out STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		ocptV 		: out STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		ovisible 	: out STD_LOGIC;
		osynchroH 	: out STD_LOGIC;
		osynchroV 	: out STD_LOGIC
		);
end component hdmi_trame;

component hdmi_interface is
	port (
		clkpixel 	: in STD_LOGIC;
		clkdata 	: in STD_LOGIC;
		videoenable 	: in STD_LOGIC ;
		imagevisible	: in STD_LOGIC;
		isynchroH 	: in STD_LOGIC;
		isynchroV 	: in STD_LOGIC;
		irouge 		: in STD_LOGIC_VECTOR(7 downto 0);
		ivert		: in STD_LOGIC_VECTOR(7 downto 0);
		ibleu 		: in STD_LOGIC_VECTOR(7 downto 0);
		ohdmi_clk	: out STD_LOGIC;
		ohdmi_datas 	: out STD_LOGIC_VECTOR(2 downto 0) -- inversion des rouge et bleu
		);
end component hdmi_interface;

component hdmi_image is
	port (
		clk 	: in STD_LOGIC;
		ienable : in STD_LOGIC ;
		icptH 	: in STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		icptV 	: in STD_LOGIC_VECTOR(11 downto 0); -- 12 bits pour toutes les résolutions
		orouge	: out STD_LOGIC_VECTOR(7 downto 0);
		overt 	: out STD_LOGIC_VECTOR(7 downto 0);
		obleu 	: out STD_LOGIC_VECTOR(7 downto 0)
		);
end component hdmi_image;

-- horloges
signal horlogesreset, horlogesclkin, horlogeslocked: std_logic ;
signal clkpixel , clkhdmidatas : std_logic;
-- trames
signal posH		: std_logic_vector(11 downto 0);
signal posV 		: std_logic_vector(11 downto 0);
signal video_enable 	: std_logic ;
signal ImageVisible 	: std_logic;
signal ImageSynchroH 	: std_logic ;
signal ImageSynchroV 	: std_logic ;
-- couleurs pixel
signal pixrouge, pixvert, pixbleu : std_logic_vector(7 downto 0);

begin

	horlogesclkin <= iCLK ;
	horlogesreset <= not iRESETn ;
	video_enable <= horlogeslocked and iHDMI_HPD ;
	chiphorloges : hdmi_horloges port map (areset => horlogesreset , inclk0 => horlogesclkin, locked => horlogeslocked, 
						c0 => clkpixel , c1 => clkhdmidatas );
										  
	chiptrames : hdmi_trame port map (clk => clkpixel , ienable => video_enable ,ocptH => posH, 
					ocptV => posV , ovisible => ImageVisible ,
					osynchroH => ImageSynchroH , osynchroV => ImageSynchroV	);	
	
	chipinterface : hdmi_interface port map ( clkpixel => clkpixel , clkdata => clkhdmidatas , videoenable => video_enable,
						imagevisible => ImageVisible, isynchroH => ImageSynchroH , isynchroV => ImageSynchroV,
						irouge => pixrouge, ivert => pixvert , ibleu => pixbleu,
						ohdmi_clk => oHDMI_CLK , ohdmi_datas => oHDMI_TX );
	-- image
	chipimage : hdmi_image port map ( clk => clkpixel , ienable => ImageVisible ,
					icptH => posH , icptV => posV ,
					orouge => pixrouge , overt => pixvert , obleu => pixbleu );
											
	
end arch_hdmi_base;